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advance information 18-mb pipelined mcm with qdr tm architecture cym52kqt36av25 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05041 rev. ** revised august 15, 2001 features ? separate independent read and write data ports ? supports concurrent transactions 167 mhz clock for high bandwidth ? 2.5 ns clock-to-valid access time double data rate (ddr) interfaces on both read & write ports (data transferred at 333 mhz) @167 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two output clocks (c and c ) account for clock skew and flight time mismatches single multiplexed address input bus latches address inputs for both read and write ports separate port selects for depth expansion synchronous internally self-timed writes 2.5v core power supply with hstl inputs and outputs 13x15 mm, 1.0-mm pitch fbga package, 165 ball (11x15 matrix) variable drive hstl output buffers expanded hstl output voltage (1.4v?1.9v) jtag interface variable impedance hstl functional description the cym52kqt36av25 is a 2.5v 18m synchronous pipe- lined sram equipped with qdr architecture. qdr architec- ture consists of two separate ports to access the memory ar- ray. the read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. access to each port is accom- plished through a common address bus. the read address is latched on the rising edge of the k clock and the write address is latched on the rising edge of k clock. qdr has separate data inputs and data outputs to completely eliminate the need to ? turn-around ? the data bus required with common i/o devic- es. accesses to the cym52kqt36av25 read and write ports are completely independent of one another. all accesses are initiated synchronously on the rising edge of the positive input clock (k). in order to maximize data throughput, both read and write ports are equipped with double data rate (ddr) inter- faces. therefore, data can be transferred into the device on every rising edge of both input clocks (k and k ) and out of the device on every rising edge of the output clock (c and c ) there- by maximizing performance while simplifying system design. depth expansion is accomplished with a port select input for each port. each port select allows each port to operate inde- pendently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c input clocks. writes are con- ducted with on-chip synchronous self-timed write circuitry. logic block diagram a (17:0) k k d [35:0] wps bws 0 vref 18 bws 1 18 18 36 d [17:0] d [17:0] a (17:0) c c bws 2 bws 3 k k c c k k c c a (17:0) rps q [35:0] q [17:0] q [17:0] rps rps q [8:0] q [17:9] q [25:18] q [35:26] d [8:0] d [17:9] d [25:18] d [35:26] tdo tms tclk tdi tdo tms tclk tdi tclk tms tdi tdo
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 2 of 25 selection guide cym52kqt36av25 -167 cym52kqt36av25 -133 cym52kqt36av25 -100 maximum operating frequency (mhz) 167 133 100 maximum operating current (ma) tbd tbd tbd pin configuration - cym52kqt36av25 (top view) 1 2 3 4 5 6 7 8 9 10 11 a nc vss nc wps bws 2 k bws 1 rps nc vss nc b q27 q18 d18 a bws 3 k bws 0 a d17 q17 q8 c d27 q28 d19 vss a a a vss d16 q7 d8 d d28 d20 q19 vss vss vss vss vss q16 d15 d7 e q29 d29 q20 vddq vss vss vss vddq q15 d6 q6 f q30 q21 d21 vddq vdd vss vdd vddq d14 q14 q5 g d30 d22 q22 vddq vdd vss vdd vddq q13 d13 d5 h nc vref vddq vddq vdd vss vdd vddq vddq vref zq j d31 q31 d23 vddq vdd vss vdd vddq d12 q4 d4 k q32 d32 q23 vddq vdd vss vdd vddq q12 d3 q3 l q33 q24 d24 vddq vss vss vss vddq d11 q11 q2 m d33 q34 d25 vss vss vss vss vss d10 q1 d2 n d34 d26 q25 vss a a a vss q10 d9 d1 p q35 d35 q26 a a c a a q9 d0 q0 r tdo tck a a a c a a a tms tdi
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 3 of 25 pin definitions name i/o description d [35:0] input- synchronous data input signals, sampled on the rising edge of k and k clocks during valid write operations. wps input- synchronous write port select, active low. sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. deasserting will deselect the write port. deselecting the write port will cause d [35:0] to be ignored. bws 0 , bws 1, bws 2 , bws 3 input- synchronous byte write select 0, 1, 2 and 3 ? active low. sampled on the rising edge of the k and k clocks during write operations. used to select which byte is written into the device during the current portion of the write operations. bytes not written remain unaltered. bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27] . bws 0 , bws 1 , bws 2 and bws 3 are sampled on the same edge as d [35:0] . deselecting a byte write select will cause the corresponding byte of data to be ignored and not written into the device. a (17:0) input- synchronous address inputs. sampled on the rising edge of both the k and k clocks during active read and write operations. these address inputs are multiplexed for both read and write operations. the read address is latched on the rising edge of the positive input clock (k) and the write address is latched on the rising edge of the negative input clock (k ). internally, the device is organized 256k x 72. therefore, only 18 address inputs are needed to access the entire memory array.these inputs are ignored when the appro- priate port is deselected. therefore, on the rising edge of the positive input clock (k), these inputs are ignored if the read port is deselected. these inputs are ignored on the rising edge of the negative input clock (k ) when the write port is deselected. q [35:0] outputs synchronous data output signals. these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations. when the read port is deslected, q [35:0] are automatically three-stated. rps input- synchronous read port select, active low. sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting will cause the read port to be deselected. when deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the c clock. the device is organized internally as 256k x 72. each read access consists of a burst of two sequential 36-bit transfers. c input-clock positive output clock, input. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. c input-clock negative output clock, input. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. k input-clock positive input clock, input. the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [35:0] when in single clock mode. all ac- cesses are initiated on the rising edge of k. k input-clock negative input clock input. k is used to capture synchronous inputs being presented to the device and to drive out data through q [35:0] when in single clock mode. zq input output impedance matching input. this input is used to tune the device outputs to the system data bus impedance. q [35:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v dd , which enables the minimum impedance mode. this pin cannot be con- nected directly to gnd or left unconnected. tdo output tdo for jtag. tck input tck pin for jtag. tdi input tdi pin for jtag. tms input tms pin for jtag. nc not connect pins. these are not connected to the die.
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 4 of 25 introduction functional overview the cym52kqt36av25 is a synchronous pipelined burst sram equipped with both a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and out through the read port. the cym52kqt36av25 multiplexes the address inputs in order to minimize the number of address pins required. the cym52kqt36av25 latches the read address on the rising edge of the positive input clock (k) and latches the write ad- dress on the rising edge of the negative input clock (k ). by having separate read and write ports, the cym52kqt36av25 completely eliminates the need to ? turn around ? the data bus and avoids any possible data contention, thereby simplifying system design. accesses for both ports are initiated by the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the output clocks (c and c ) or k and k when in single clock mode. all synchronous data inputs (d [35:0] ) pass through input regis- ters controlled by the input clocks (k and k ). all synchronous data outputs (q [35:0] ) pass through output registers controlled by the rising edge of the output clocks (c and c ) all synchronous control inputs (rps , wps , bws 0 , bws 1 , bws 2 , bws 3 ) pass through input registers controlled by the rising edge of the input clocks (k and k ). read operations read operations are initiated by asserting rps active at the rising edge of the positive input clock (k). the address pre- sented to a [17:0] is stored in the read address register. be- cause the cym52kqt36av25 is a 72-bit memory, it will ac- cess two 36-bit data words with each read operation. following the next k clock rise the data is available to be latched out of the device, triggered by the c clock. on the following c clock rise the corresponding lower order word of data is driven onto q [36:0] . on the subsequent rising edge of c the higher order data word is driven onto q [35:0] . the requested data will be valid 2.5 ns from the rising edge of the output clock (c or c , 167 mhz device). with the separate input and output ports and the internal logic determining when the device should drive the data bus, the qdr architecture has eliminated the need for an output enable input to control the state of the out- put drivers. read accesses can be initiated on every rising edge of the positive input clock (k). doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (c and c ). the cym52kqt36av25 will deliver the most recent data for the address location being accessed. this includes forwarding data when a read and write transactions to the same address location are initiated on the same clock rise. when the read port is deselected, the cym52kqt36av25 will first complete the pending read transactions. synchronous in- ternal circuitry will automatically three-state the outputs follow- ing the next rising edge of the positive output clock (c). this will allow for a seamless transition between devices without the insertion of wait states. the cym52kqt36av25 is equipped with internal logic that synchronously controls the state of the output drivers. the log- ic inside the device determines when the output drivers need to be active or inactive. this advanced logic eliminates the need for an asynchronous output enable since the device will automatically enable/disable the output drivers during the proper cycles. the cym52kqt36av25 will automatically power-up in a deselcted state with the outputs in a three state condition. write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the same clock rise (k) the data presented to d [35:0] is stored into the lower 36-bit write data register provided bws [3:0] are all asserted active. on the subsequent rising edge of the negative input clock (k ), the information presented to a [17:0] is latched and stored in the write address register and the information pre- sented to d [35:0] is also stored into the upper 36-bit write data register provided bws [3:0] are all asserted active. the 72 bits of data are then written into the memory array at the specified location. write accesses can be initiated on every rising edge of the positive clock. doing so will pipeline the data flow such that 36 bits of data can be transferred into the device on every ris- ing edge of the input clocks (k and k ). byte write operations are supported by the cym52kqt36av25. a write operation is initiated by selecting the write port using wps . the bytes that are written are deter- mined by bws 0 , bws 1 , bws 2 and bws 3 which are sampled with each set of 36-bit data words. asserting the appropriate byte write select input during the data portion of a write will allow the data being presented to be latched and written into the device. deasserting the byte write select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read/modify/write operations to a byte write op- eration. when deselected, the write port will ignore all inputs. v ref input- reference reference voltage input. static input used to set the reference level for hstl inputs and outputs as well as a/c measurement points. v dd power supply power supply inputs to the core of the device. should be connected to 2.5v power supply. v ss ground ground for the device. should be connected to ground of the system. v ddq power supply power supply inputs for the outputs of the device. should be connected to 1.5v power supply. pin definitions (continued)
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 5 of 25 single clock mode the cym52kqt36av25 can be used with a single clock mode. in this mode the device will recognize only the pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the de- vice had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, the user must tie c and c to v dd . during pow- er-up, the device will sense the single clock input and operate in either single clock or double clock mode. the clock mode should not be changed during device operation. concurrent transactions the read and write ports on the cym52kqt36av25 operate completely independently of one another. since each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transac- tion on the other port. should the read and write ports access the same location on the rising edge of the positive input clock, the information presented to d [35:0] will be forwarded to q [35:0] such that no latency is required to access valid data. coher- ency is conducted on cycle boundaries. once the second word of data is latched into the device, the write operation is consid- ered completed. at this point, any access to that address loca- tion will receive that data until altered by a subsequent write operation. coherency is not maintained for write operations initiated in the cycle after a read. depth expansion the cym52kqt36av25 has a port select input for each port. this allows for easy depth expansion. both port selects are sampled on the rising edge of the pos- itive input clock only (k). each port select input can de- select the specified port. deselecting a port will not af- fect the other port. all pending transactions (read and write) will be completed prior to the device being dese- lected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guar- antee impedance matching with a tolerance of 10% is between 175 ? and 350 ? , with v ddq = 1.5v. the output impedance is adjusted every 1024 cycles to adjust for drifts in supply voltage and temperature. truth table [ 1,2 ] operation address used rps wps k comments deselected - h h l-h read port is deselected. outputs three-state following next rising edge of negative input clock (k ) if in single clock mode, or c if using c and c as the output clocks. write port is deselected. all write port inputs are ignored during this clock rise and the subsequent rising edge of the negative input clock (k ). begin read external l h l-h read operation initiated. addresses are stored in the read address reg- ister. following the next k clock rise the first (lower order) 36-bit word will be available to be driven out onto q [35:0] gated by the rising edge of the output clock c. on the subsequent rising edge of the negative output clock (c ) the second (higher order) 36-bit word is driven out onto q [35:0] . begin write external on next rising edge of k h l l-h write operation initiated. the information presented to d [35:0] is stored in the write data register. on the subsequent rising edge of the negative input clock (k ) the device will latch the addresses presented to a [17:0] and the data presented to d [35:0] ]. the entire 72 bits of information will then be written into the memory array. see write description table for byte write information, note: 1. x = don ? t care, h = logic high, l = logic low. 2. device will power-up deselected and the outputs in a three-state condition. 3. bws 0 and bws 1 asserted active low during all cycles. for byte write operations, see write description table. 4. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 5. it is recommended that k = k# and c = c# when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 6 of 25 write descriptions [6] operation k k bws 0 bws 1 bws 2 bws 3 comments write initiatedl-h- llllall the four bytes (d [35:0] ) are written into the lower order 36-bit write buffer device during this portion of a write operation. write complet- ed - write initi- ated on previ- ous k clock rise -l-hllllall the four bytes (d [35:0] ) are written into the higher order 36-bit write buffer device during this portion of a write operation. the contents of the entire 72-bit write buffer are written into the memory array. write initiated l-h - l h h h only byte 0 (d [8:0] ) is written into the lower order 36-bit write buffer of the device during this portion of a write operation. all the remaining data bits (d [35:9] ) remain unaltered. write complet- ed - write initi- ated on previ- ous k clock rise - l-h l h h h only byte 0 (d [8:0] ) is written into the higher order 36-bit write buffer of the device during this portion of a write operation. all the remaining data bits(d [35:9] ) remain unaltered. byte 0 is then written into the memory array. write initiated l-h - h l h h only byte 1 (d [17:9] ) is written into the lower order 36-bit write buffer of the device during this portion of a write operation. all the remaining data bits remain unaltered write complet- ed - write initi- ated on previ- ous k clock rise - l-h h l h h only byte 1 (d [17:9] ) is written into the higher order 36-bit write buffer of the device during this portion of a write operation. all the remaining data bits remain unaltered. byte 1 is then written into the memory array. write initiated l-h - h h l h only byte 2 (d [26:18] ) is written into the lower order 36-bit write buffer of the device during this portion of a write operation. all the remaining data bits remain unaltered. write complet- ed - write initi- ated on previ- ous k clock rise -l-hlhlhonly byte 2 (d [26:18] ) is written into the higher order 36-bit write buffer of the device during this portion of a write operation. all the remaining data bits remain unaltered. byte 2 is then written into the memory array. write initiated l-h - h h h l only byte 1 (d [35:27] ) is written into the lower order 36-bit write buffer of the device during this portion of a write operation. all the remaining data bits remain unaltered write complet- ed - write initi- ated on previ- ous k clock rise - l-h h h h l only byte 1 (d [35:27] ) is written into the higher order 36-bit write buffer of the device during this portion of a write operation. all the remaining data bits remain unaltered. byte 3 is then written into the memory array. write - no-opl-h- hhhhno data is written into the device during this portion of a write operation. write - no-op-l-hhhhhno data is written into the device during this portion of a write operation. note: 6. assumes a write cycle was initiated per the write port cycle description truth table. bws 0 , bws 1 , bws 2 and bws 3 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 7 of 25 ieee 1149.1 serial boundary scan (jtag ? fbga only) the cym52kqt36av25 incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1900, but does not have the set of func- tions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec stan- dard 2.5v i/o logic levels. disabling the jtap feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) - test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the regis- ters and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruc- tion that is loaded into the tap instruction register. for infor- mation on loading the instruction register, see the tap control- ler state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is con- nected to the most significant bit (msb) on any register. test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see tap controller state di- agram). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is oper- ating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuit- ry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruc- tion register. this register is loaded when it is placed between the tdi and tdo pins as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as de- scribed in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register defi- nitions table. tap instruction set eight different instructions are possible with the three-bit in- struction register. all combinations are listed in the instruction codes table. three of these instructions are listed as re- served and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller can- not be used to load address, data or control signals into the sram and cannot preload the input or output buffers. the sram does not implement the 1149.1 commands extest or
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 8 of 25 intest or the preload portion of sample / preload; rather it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap control- ler needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be ex- ecuted whenever the instruction register is loaded with all 0s. extest is not implemented in the cym52kqt36av25 tap controller, and therefore this device is not compliant to the 1149.1 standard. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample / preload instruction has been loaded. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap con- troller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. sample / preload sample / preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the cym52kqt36av25 tap controller is not fully 1149.1 com- pliant. when the sample / preload instructions is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will under- go a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller ? s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample / preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the k, k , c and c captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update-dr state while performing a sample / preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction reg- ister and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advan- tage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 9 of 25 tap controller state diagram test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 note: the 0/1 next to each state represents the value at tms at the rising edge of tck. 0
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 10 of 25 tap controller block diagram 0 0 1 2 . . 29 30 63 boundary scan register identification register 0 1 2 . . . . 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms 137 tap electrical characteristics over the operating range [7, 8] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma 1.7 v v oh2 output high voltage i oh = ? 100 a 2.1 v v ol1 output low voltage i ol = 2.0 ma 0.7 v v ol2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage -0.3 0.7 v i x input and output load current gnd v i v ddq ? 5 5 a notes: 7. all voltage referenced to ground 8. overshoot: v ih (ac)< v dd +1.5v for t< t tcyc /2, undershoot:v il (ac)< 0.5v for t< t tcyc /2, power-up: vih<2.6v and vdd<2.4v and vddq<1.4v for t<200ms. 9. these characteristic pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics table
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 11 of 25 tap ac switching characteristics over the operating range [10, 11] param description min. max. unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns notes: 10. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 12 of 25 tap timing and test conditions [11] (a) tdo c l =20pf z 0 =50 ? gnd 1.25v test clock test mode select tck tms test data-in tdi test data-out tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov 50 ? 2.5v 0v all input pulses 1.25v
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 13 of 25 identification register definitions instruction field value description cym52kqt36av25 revision number (63:61) 000 version number. cypress device id (60:44) 01011010010010110 defines the type of sram. cypress jedec id (43:33) 00000110100 allows unique identification of sram vendor. id register presence (32) 1 indicate the presence of an id register. revision number (31:29) 000 version number. cypress device id (28:12) 01011010010010110 defines the type of sram. cypress jedec id (11:1) 00000110100 allows unique identification of sram vendor. id register presence (0) 1 indicate the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 64 boundary scan 138
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 14 of 25 instruction codes instruction code description extest 000 captures the input/output ring contents. places the boundary scan register between the tdi and tdo. this instruction is not 1149.1 com- pliant. the extest command implemented by the ccym52kqt36av25 device will not place the output buffers into a high-z condition. if the output buffers need to be high-z con- dition, this can be accomplished by deselcting the read port. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram opera- tion. sample z 010 captures the input/output contents. places the boundary scan register between tdi and tdo. the samplez command implemented by the ccym52kqt36av25 device will place the output buffers into a high-z condition. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. boundary scan order (#1 exits device first) bit # signal name bump id 1 c 6r 2 c 6p 3 a 6n 4 a 7p 5 a 7n 6 a 7r 7 a 8r 8 a 8p 9 a 9r 10 d0 10p 11 q0 11p 12 d1 11n 13 q1 10m 14 d2 11m 15 q2 11l 16 d3 10k 17 q3 11k 18 d4 11j 19 zq 11h 20 q4 10j 21 d5 11g 22 q5 11f 23 d6 10e 24 q6 11e 25 d7 11d 26 q7 10c 27 d8 11c 28 q8 11b 29 reserved 12a (don ? t care) 30 gnd/72m 10a 31 nc/18m(1) 9a (read as 1, 18mb) 32 a 8b 33 a 7c 34 a 6c boundary scan order (#1 exits device first) (continued) bit # signal name bump id
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 15 of 25 35 rps 8a 36 bws0 7b 37 k 6b 38 k 6a 39 bws1 5a 40 wps 4a 41 a 5c 42 a 4b 43 nc/36m(1) 3a 44 gnd/144m 2a 45 reserved 1a (don ? t care) 46 d9 3b 47 q9 2b 48 d10 3c 49 q10 3d 50 d11 2d 51 q11 3e 52 d12 3f 53 q12 2f 54 d13 2g 55 q13 3g 56 d14 3j 57 q14 3k 58 d15 3l 59 q15 2l 60 d16 3m 61 q16 3n 62 d17 2n 63 q17 3p 64 a 3r 65 a 4r 66 a 4p 67 a 5p 68 a 5n boundary scan order (#1 exits device first) (continued) bit # signal name bump id 69 a 5r 70 c 6r 71 c 6p 72 a 6n 73 a 7p 74 a 7n 75 a 7r 76 a 8r 77 a 8p 78 a 9r 79 d0 10p 80 q0 11p 81 d1 11n 82 q1 10m 83 d2 11m 84 q2 11l 85 d3 10k 86 q3 11k 87 d4 11j 88 zq 11h 89 q4 10j 90 d5 11g 91 q5 11f 92 d6 10e 93 q6 11e 94 d7 11d 95 q7 10c 96 d8 11c 97 q8 11b 98 reserved 12a (don ? t care) 99 gnd/72m 10a 100 nc/18m(1) 9a (read as 1, 18mb) 101 a 8b 102 a 7c 103 a 6c 104 rps 8a boundary scan order (#1 exits device first) (continued) bit # signal name bump id
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 16 of 25 105 q2 11l 106 d3 10k 107 q3 11k 108 d4 11j 109 zq 11h 110 q4 10j 111 d5 11g 112 q5 11f 113 d6 10e 114 q6 11e 115 d7 11d 116 q7 10c 117 d8 11c 118 q8 11b 119 reserved 12a (don ? t care) 120 gnd/72m 10a 121 nc/18m(1) 9a (read as 1, 18mb) 122 a 8b boundary scan order (#1 exits device first) (continued) bit # signal name bump id 123 a 7c 124 a 6c 125 rps 8a 126 q4 10j 127 d5 11g 128 q5 11f 129 d6 10e 130 q6 11e 131 d7 11d 132 q7 10c 133 d8 11c 134 q8 11b 135 reserved 12a (don ? t care) 136 gnd/72m 10a 137 nc/18m(1) 9a (read as 1, 18mb) 138 a 8b boundary scan order (#1 exits device first) (continued) bit # signal name bump id
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 17 of 25 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage on v dd relative to gnd ....... ? 0.5v to +3.6v dc voltage applied to outputs in high z state [12] ............................... ? 0.5v to v ddq + 0.5v dc input voltage [12] ............................ ? 0.5v to v ddq + 0.5v current into outputs (low) ........................................ 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature [13] v dd v ddq com ? l 0 c to +70 c 2.5v100mv 1.4v to 1.9v electrical characteristics over the operating range parameter description test conditions min. max. unit v dd power supply voltage 2.4 2.6 v v ddq i/o supply voltage 1.4 1.9 v v oh output high voltage i oh = ? 2.0 ma, nominal impedance v ddq /2 + 0.3 v ddq v v ol output low voltage i ol = 2.0 ma, nominal impedance v ss v ddq /2 ? 0.3 v v ih input high voltage v ref + 0.1 v ddq +0.3 v v il input low voltage [12] ? 0.3 v ref ? 0.1 v i x input load current gnd v i v ddq ? 5 5 a i oz output leakage current gnd v i v ddq, output disabled ? 5 5 a v ref input reference volt- age typical value = 0.75v 0.68 0.9 v i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 6.0-ns cycle, 167 mhz 800 ma 7.5-ns cycle, 133 mhz 600 ma 10-ns cycle, 100 mhz 500 ma i sb1 automatic power-down current max. v dd , both ports de- selected, v in v ih or v in v il f = f max = 1/t cyc , in- puts static 6.0-ns cycle, 167 mhz 100 ma 7.5-ns cycle, 133 mhz 80 ma 10-ns cycle, 100 mhz 60 ma note: 12. minimum voltage equals ? 2.0v for pulse duration less than 20 ns. 13. t a is the ? instant on ? case temperature.
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 18 of 25 switching characteristics over the operating range [14,15,16] -167 -133 -100 parameter description min. max. min. max. min. max. unit t cyc k clock and c clock cycle time 6.0 7.5 10.0 ns t kh input clock (k/k and c/c ) high 2.4 3.2 3.5 ns t kl input clock (k/k and c/c ) low 2.4 3.2 3.5 ns t khkh k/k clock rise to k /k clock rise and c/c to c/c rise (rising edge to rising edge) 2.7 3.3 3.4 4.1 4.4 5.4 ns t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 2.0 0.0 2.5 0.0 3.0 ns t co c/c clock rise (or k/k in single clock mode) to data valid [15] 2.5 3.0 3.0 ns t doh data output hold after output c/c clock rise (active to active) 1.2 1.2 1.2 ns set-up times t sa address set-up to clock (k and k ) rise 0.7 0.8 1.0 ns t sc control set-up to clock (k and k ) rise (rps , wps , bws 0 , bws 1 ) 0.7 0.8 1.0 ns t sd d [17:0] set-up to clock (k and k ) rise 0.7 0.8 1.0 ns hold times t ha address hold after clock (k and k ) rise 0.7 0.8 1.0 ns t hc control hold after clock (k and k ) rise (rps , wps , bws 0 , bws 1 ) 0.7 0.8 1.0 ns t hd d [17:0] hold after clock (k and k ) rise 0.7 0.8 1.0 ns output times t chz clock (c and c ) rise to high-z (active to high-z) [15, 16] 2.5 3.0 3.0 ns t clz clock (c and c ) rise to low-z [15, 16] 1.2 1.2 1.2 ns notes: 14. unless otherwise noted, test conditions assume signal transition time of 2v/ns, timing reference levels of 0.75v,vref = 0.75 v, rq = 250 ? , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. 15. t chz , t clz , are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 100 mv from steady-state voltage. 16. at any given voltage and temperature t chz is less than t clz and, t chz less than t co .
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 19 of 25 capacitance [17] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 2.5v. v ddq = 1.5v tbd pf c clk clock input capacitance tbd pf c o output capacitance tbd pf ac test loads and waveforms note: 17. tested initially and after any design or process change that may affect these parameters. 1.25v 0.25v r=50 ? 5pf including jig and scope all input pulses device r l =50 ? z 0 =50 ? v ref =0.75v v ddq /2 [14] 0.75v under te st v ddq /2 device under te s t output v ddq /2 v ref v ref output (a) rq= 250 ? (b) rq= 250 ? zq zq
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 20 of 25 switching waveforms k = don ? t care = undefined read/deselect sequence k a [17:0] data out rps b a q(a) q(a+1) q(b) q(b+1) c q(c) q(c+1) t kh t kl t cyc t sa t ha t sc t hc t chz t kh t kl t khkh t doh device originally deselected. t khkh c c t co t co t khch t doh t clz activity on the write port is unknown.
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 21 of 25 switching waveforms (continued) k = don ? t care = undefined bws x is both bws 0 and bws 1 write/deselect sequence k a [17:0] data in wps b a d(a) d(a+1) d(b) d(b+1) c t kh t kl t cyc t sa t ha t sc t hc d(c) d(c+1) t hd t sd c and c reference to data outputs and do not affect writes. activity on the bws x t sc t hc t kl read port is unknown. bws x low=valid, byte writes allowed, see byte write table for details.
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 22 of 25 switching waveforms (continued) k wps = don ? t care = undefined any port select can deselect the port. read/write/deselect sequence k a [17:0] q [35:0] rps d [35:0] read port previously deselected. d c g b e b a q(e) q(e+1) d(a+1) d(b) d(b+1) d(d) d(d+1) d(c) d(c+1) q(b) q(b+1) q(g) q(g+1) d(a) write data forwarded c c bws [1:0] both assumed active. bws x
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 23 of 25 i ordering information speed (mhz) ordering code package name package type operating range 167 CYM52KQT36AV25-16BBC bb165b 13 x 15 mm fbga commercial 133 cym52kqt36av25-13bbc bb165b 13 x 15 mm fbga commercial 100 cym52kqt36av25-10bbc bb165b 13 x 15 mm fbga commercial part numbering scheme cy m depth architecture width revision voltage speed package temperature cypress module module depth (1m) architecture (qt - qdr, burst of 2) bus width (36 bits) module revision (a-first revision) core/io voltage (cd ? 2.5v/1.5hstl) frequency (100 ? 133 mhz) bb - 165fbga c - commercial
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 24 of 25 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 165-ball fbga (13 x 15 x 1.62 mm) bb165b 51-49026-**
cym52kqt36av25 advance information document #: 38-05041 rev. ** page 25 of 25 document title: cym52kqt36av25 18-mb pipelined mcm with qdr architecture document number: 38-05041 rev. ecn no. issue date orig. of change description of change ** 106920 08/20/01 meg new data sheet

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